Circuit patterns on electronic components such as a semiconductor element are made by using an exposure technology, for example, by reductively projecting a negative circuit pattern formed on a photo mask to a silicon wafer. To promote miniaturization of electronic components, the wavelength of light used in exposure technology becomes shorter and shorter. Recently, an EUV exposure technology using an EUV (Extreme Ultraviolet) light as the exposure light has been developed. A photo mask for the EUV exposure is structured such that a multi-layered film including metal and a semiconductor for reflecting EUV light is provided on a mask blank (substrate material) and a negative circuit pattern including a light absorber is formed on the multi-layered film. A mask blank is manufactured by chemical mechanical polishing (CMP) of a glass substrate. Defects on a surface of a mask blank cause defects in a multi-layered film and lead to deterioration in precision of a negative circuit pattern. Accordingly, when manufacturing the mask blank by means of CMP, there is a need to prevent the defects, if possible. In this regard, Japanese Laid-Open Patent Publication No. 2004-310067 discloses a technology of measuring a surface contour of a glass substrate before a polishing process and performing a process of improving the flatness of the surface of the glass substrate based on the measurement result.